madmo/dsi85
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  • ddab3a9767 add documentation Konrad Anton 2017-05-18 14:16:33 +0200
  • 0ae87cb318 make LVDS regs 0x19..0x1B configurable by DT Konrad Anton 2017-05-18 13:47:55 +0200
  • 59616c830f Reimplement dsi85 as DRM bridge (squashed). (#1) master awinia 2017-05-18 11:27:11 +0200
  • c794c33c38 fix computation of dsi_clk_divider Konrad Anton 2017-05-17 19:41:18 +0200
  • 78b77cfd52 Derive sync polarity from panel's flags Konrad Anton 2017-05-17 19:30:38 +0200
  • 4e5506cbe5 use DRM logging macros uniformly Konrad Anton 2017-05-17 18:54:44 +0200
  • a92650f67a remove bridge_mode_fixup debug helper Konrad Anton 2017-05-17 16:09:50 +0200
  • 0bf5dac1ee add DT attrs for more DSI85 registers Konrad Anton 2017-05-17 16:08:59 +0200
  • 6bacc5bf00 add debugging mode_fixup handler to bridge Konrad Anton 2017-05-17 14:48:45 +0200
  • 711c5d8fd2 compute DSI input clock from DT attributes and mode Konrad Anton 2017-05-17 14:48:04 +0200
  • 9267393b6d Compute DSI85 register values from Panel Konrad Anton 2017-05-16 19:24:34 +0200
  • 73993839b2 Reimplement dsi85 as DRM bridge (squashed). Konrad Anton 2017-04-07 17:54:45 +0200
  • 241f587f41 update dsi rate for fixed dsi clock Moritz Bitsch 2017-03-29 14:45:39 +0200
  • ed061181c4 fix pixel rate for dsi Moritz Bitsch 2017-03-08 09:35:59 +0100
  • a226fe4fcb add testpattern registers for 1920x1080 Moritz Bitsch 2017-02-27 15:17:09 +0100
  • e25c6b0018 use reviewed values Moritz Bitsch 2017-02-16 16:14:39 +0100
  • 00ce924477 use timings for 445Mhz dsi clock Moritz Bitsch 2017-02-15 10:52:42 +0100
  • 7e0409fff6 Prepare for normal operation Moritz Bitsch 2017-02-08 14:38:38 +0100
  • 068c5ac881 use external ref clock Moritz Bitsch 2017-02-08 12:55:05 +0100
  • 6a759173c5 clean up code Moritz Bitsch 2017-02-08 11:34:39 +0100
  • 4aef94c064 initial import of dsi85 driver Moritz Bitsch 2017-02-06 16:03:41 +0100