* Reimplement dsi85 as DRM bridge (squashed).
- blunt import of preliminary bridge driver
- make dsi85 a kernel extension instead of a module to circumvent problems
with DRM init order
- make i2c matchstring match our DTS
- find and use associated drm_panel
- add hardcoded DSI85 init in bridge-enable
- Do not drm_connector_register yet at bridge_attach time (unlike
other bridge drivers)
- Add a mipi_dsi_device to configure #lanes
The DSI host wants to know the number of lanes, and guesses 1 lane if
not given. The old attempt using just panel-simple was easy; a panel
declared as DSI panel in panel-simple gets a mipi_dsi_device which it
can configure.
This driver follows the example of the adv7533 driver and creates its
own mipi_dsi_device, where it places a hard-coded number of lanes.
- cleanup
* Compute DSI85 register values from Panel
At bridge_mode_set time, fill all logical DSI85 registers from panel
parameters and constant assumptions, then write logical registers to
physical registers.
Still needs override for a few logical registers: related to DSI
clock, and related to horizontal parameters which our panel_simple
contains with factor 2 to force proper DSI timings.
* compute DSI input clock from DT attributes and mode
* add debugging mode_fixup handler to bridge
* add DT attrs for more DSI85 registers
sync delay, DSI clock divider.
And cleanup.
* remove bridge_mode_fixup debug helper
* use DRM logging macros uniformly
* Derive sync polarity from panel's flags
but make sure that DSI always uses standard polarity; fix that in the
mode_fixup callback.
* fix computation of dsi_clk_divider
Code assumed wrong bit position in 0x0B, but with the right bit
position, the divider is trivial to compute from existing
params. There goes one DT attribute.
* make LVDS regs 0x19..0x1B configurable by DT
* add documentation
