Reimplement dsi85 as DRM bridge (squashed). (#1)
* Reimplement dsi85 as DRM bridge (squashed). - blunt import of preliminary bridge driver - make dsi85 a kernel extension instead of a module to circumvent problems with DRM init order - make i2c matchstring match our DTS - find and use associated drm_panel - add hardcoded DSI85 init in bridge-enable - Do not drm_connector_register yet at bridge_attach time (unlike other bridge drivers) - Add a mipi_dsi_device to configure #lanes The DSI host wants to know the number of lanes, and guesses 1 lane if not given. The old attempt using just panel-simple was easy; a panel declared as DSI panel in panel-simple gets a mipi_dsi_device which it can configure. This driver follows the example of the adv7533 driver and creates its own mipi_dsi_device, where it places a hard-coded number of lanes. - cleanup * Compute DSI85 register values from Panel At bridge_mode_set time, fill all logical DSI85 registers from panel parameters and constant assumptions, then write logical registers to physical registers. Still needs override for a few logical registers: related to DSI clock, and related to horizontal parameters which our panel_simple contains with factor 2 to force proper DSI timings. * compute DSI input clock from DT attributes and mode * add debugging mode_fixup handler to bridge * add DT attrs for more DSI85 registers sync delay, DSI clock divider. And cleanup. * remove bridge_mode_fixup debug helper * use DRM logging macros uniformly * Derive sync polarity from panel's flags but make sure that DSI always uses standard polarity; fix that in the mode_fixup callback. * fix computation of dsi_clk_divider Code assumed wrong bit position in 0x0B, but with the right bit position, the divider is trivial to compute from existing params. There goes one DT attribute. * make LVDS regs 0x19..0x1B configurable by DT * add documentation
This commit is contained in:
awinia
Moritz Bitsch
parent
241f587f41
commit
59616c830f
7
Kconfig
Normal file
7
Kconfig
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@ -0,0 +1,7 @@
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config DRM_BRIDGE_DSI85
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tristate "DSI85 DSI-to-LVDS bridge"
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depends on OF
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select DRM_KMS_HELPER
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select REGMAP_I2C
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help
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Support for the DSI85 DSI-to-LVDS-bridge.
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13
Makefile
13
Makefile
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@ -1,11 +1,2 @@
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ifneq ($(KERNELRELEASE),)
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# kbuild part of makefile
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include Kbuild
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else
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# normal makefile
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KDIR ?= /lib/modules/`uname -r`/build
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default:
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$(MAKE) -C $(KDIR) M=$$PWD
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endif
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obj-$(CONFIG_DRM_BRIDGE_DSI85) := dsi85.o
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dsi85-y := dsi85_main.o
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269
dsi85.txt
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269
dsi85.txt
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@ -0,0 +1,269 @@
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dsi85 DSI-to-LVDS bridge driver
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###############################
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This driver integrates the TI SN65DSI85 DSI-to-LVDS converter into a
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DRM-based graphics setup.
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Author: Konrad Anton <konrad.anton@awinia.de>
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for Hella-Gutmann Solutions GmbH.
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Setup
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=====
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In order to use dsi85 in a project, copy the dsi85 tree to
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drivers/gpu/drm/bridge/dsi85 (the "dsi85" buildroot package does that)
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and set CONFIG_DSI85=y.
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The dsi85 driver implements a DRM Bridge which sits between a DSI
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output and a Panel. The Panel knows panel timings and how to switch
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the backlight. Usually, the panel-simple driver is a good choice.
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Configuration by DT
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-------------------
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Dsi85 needs three nodes in the Device Tree: the dsi85 node, the Panel
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node and the DSI node. As an I2C client, the dsi85 node wants to be
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nested in the node of the I2C bus::
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i2c@12460000 {
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//...
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dsi85@2d {
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compatible = "ti,dsi85"; /* instantiate the dsi85 driver */
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reg = <0x2d>; /* i2c slave id */
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dsi-lanes = <4>; /* tuning parameters -- see below */
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lvds-channels = <2>;
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sync-delay = <33>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi85_in: endpoint {
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remote-endpoint = <&dsi0_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi85_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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};
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The dsi85 node must have exactly two ports. Port 0 points toward the
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DSI output, Port 1 toward the Panel. The DSI output needs a port wired
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to dsi85_in. In the Qualcomm MSM example::
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dsi0: mdss_dsi@4700000 {
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status = "okay";
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vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/
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/* ... */
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ports {
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port@0 {
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reg = <0> ;
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dsi0_in: endpoint {
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remote-endpoint = <&mdp_dsi1_out>;
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};
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};
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port@1 {
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reg = <1> ;
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dsi0_out: endpoint {
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remote-endpoint = <&dsi85_in>;
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data-lanes = <0 1 2 3>;
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};
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};
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};
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};
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On the other side, the panel needs a port wired to dsi85_out::
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dsi_lvds_panel: panel {
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reg = <0>;
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compatible = "nlt,192108AC18"; /* one of panel-simple's
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match strings */
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backlight = <&backlight>;
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vddp-supply = <&pm8921_l17>;
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iovcc-supply = <&pm8921_lvs7>;
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enable-gpios = <&tlmm_pinmux 80 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&tlmm_pinmux 32 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&display_pins>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&dsi85_out>;
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};
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};
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};
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Tuning parameters
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-----------------
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Some of the configuration details of a DSI85 can be controlled by
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setting properties inside the dsi85 DT node. See DSI85 datasheet for
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more information.
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dsi-lanes = N
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number of DSI lanes to use. Only tested with 4.
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lvds-channels = N
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number of LVDS channels to use. (Only tested with 2).
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sync-delay = N
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Additional delay to insert when translating a DSI HSync or VSync to
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a LVDS Hsync or VSync. Becomes DSI85 registers CHA_SYNC_DELAY_LOW/HIGH,
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see there. Default 0.
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de-neg-polarity = 0 or 1
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default 0; when 1, set DE_NEG_POLARITY=1 in 0x18.7
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force-24bpp-mode = 0 or 1
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Default 0. Controls CHA_24BPP_MODE and
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CHB_24BPP_MODE: If 1, force 24bpp; if 0, force 18bpp.
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force-24bpp-format1 = 0 or 1
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Default 0. Controls CHA_24BPP_FORMAT1 and CHB_24BPP_FORMAT1, see there.
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lvds-vocm = 0..3
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Default 0. Bit 1 controls CHA_LVDS_VOCM and Bit 0 controls CHB_LVDS_VOCM, see there.
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false means 1.2V, true means 0.9V.
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lvds-vod-swing-cha = 0..3
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Default 0. Controls the CHA_LVDS_VOD_SWING field.
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lvds-vod-swing-chb = 0..3
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Default 0. Controls the CHB_LVDS_VOD_SWING field.
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lvds-even-odd-swap = 0 or 1
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Default 0. Controls EVEN_ODD_SWAP.
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lvds-reverse = 0..3
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Default 0. Bit 0 controls CHB_REVERSE_LVDS, and Bit 1 controls CHA_REVERSE_LVDS.
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lvds-term = 0..3
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Default 3. Bit 0 controls CHB_LVDS_TERM (true means termination on),
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and Bit 1 controls CHA_LVDS_TERM.
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lvds-cm-adjust-cha = 0..3
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Default 0. Adjust common mode voltage for channel A, 0 means don't adjust.
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See CHA_LVDS_CM_ADJUST.
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lvds-cm-adjust-chb = 0..3
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Default 0. Adjust common mode voltage for channel B, 0 means don't adjust.
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See CHB_LVDS_CM_ADJUST.
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Other parameters
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----------------
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The Panel will require a certain polarity of HSYNC and VSYNC
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signals. These are configured in the drm_display_mode instance of the
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panel-simple panel object, along with the display timings::
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static const struct drm_display_mode nlt_192108AC18_mode = {
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.clock = 74175 * 2,
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.hdisplay = 960 * 2,
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.hsync_start = (960 + 48) * 2,
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.hsync_end = (960 + 48 + 44) * 2,
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.htotal = (960 + 48 + 44 + 48) * 2,
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.vdisplay = 1080,
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.vsync_start = 1080 + 15,
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.vsync_end = 1080 + 15 + 15,
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.vtotal = 1080 + 15 + 15 + 15,
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.vrefresh = 60,
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.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
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};
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The flags bit DRM_MODE_FLAG_NVSYNC causes VS_NEG_POLARITY=1 in DSI85
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reg 0x18, i.e. VS is negative polarity driven 0 during corresponding
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sync. Analogously, DRM_MODE_FLAG_NHSYNC causes HS_NEG_POLARITY=1 in
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reg 0x18 for HSync. Default is VS_NEG_POLARITY=HS_NEG_POLARITY=0.
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Notes for dual-channel LVDS
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---------------------------
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The NL192108AC18 panel's datasheet requests a clock of 74MHz and a
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width of 960 double-pixel clocks. However, dsi85 expects the panel to
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contain pixel timings, i.e. 148MHz and 1920 pixels width, because then
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the DSI output can be configured directly from the panel parameters.
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Debug messages
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--------------
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The dsi85 driver uses the DRM logging facility which can be controlled
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by kernel parameter drm.debug=N, where N=0x3f enables all output.
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Especially errors in the Device Tree configuration can be discovered
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that way; grep for "dsi85".
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Design and Implementation
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=========================
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Implementation follows the example of other bridge drivers in the
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mainline kernel, especially nxp-ptn3460.
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The dsi85 driver is implemented as an I2C client driver whose probe
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method tries to locate panel and DSI drivers. Depending on
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circumstances, this will fail if some of the other drivers (e.g. the
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panel) are not yet ready. In that case, the probe callback uses the
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EPROBE_DEFER mechanism to request a retry. Otherwise, the probe
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callback installs the DRM bridge represented by sn65dsi85_bridge_funcs.
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The first bridge callback is the attach callback, which assembles a
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driver graph out of:
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- a DRM Connector, implemented using drm_connector_helper, that helps
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choose display modes by delegating to the Panel.
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- the DRM Encoder supplied by the DRM framework
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- a DSI client device to configure DSI parameters (number of lanes...)
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The other callbacks deal with a proper sequence of initialization:
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- mode_fixup adjusts a display mode and decides whether it can be
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activated. The dsi85 implementation does not attempt to validate
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whether the timings are possible -- in the intended setting, the
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panel does not change that often -- but it normalizes the
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sync-polarity flags so that DSI always uses the same sync polarity,
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regardless of the panel's choice.
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- mode_set is the place where the DSI85 register values are computed
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according to the adjusted display mode and the DT settings, then
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written to DSI85.
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- pre_enable tells the panel to power itself up
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- enable enables the DSI85 PLL and tells the panel to activate its backlight
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- disable undoes enable
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- post_disable undoes pre_enable
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Caveats
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-------
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The dsi85 driver has only been tested in a Qualcomm MSM kernel, and
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only with the panel NL192108AC18, dual-channel LVDS, four-lane DSI.
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972
dsi85_main.c
972
dsi85_main.c
File diff suppressed because it is too large
Load diff
46
dsi85_registers.h
Normal file
46
dsi85_registers.h
Normal file
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@ -0,0 +1,46 @@
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#ifndef DSI85_REGISTERS_H_INCLUDED
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#define DSI85_REGISTERS_H_INCLUDED
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/* Register addresses */
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#define DSI85_SOFT_RESET 0x09
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#define DSI85_CORE_PLL 0x0A
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#define DSI85_PLL_DIV 0x0B
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#define DSI85_PLL_EN 0x0D
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#define DSI85_DSI_CFG 0x10
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#define DSI85_DSI_EQ 0x11
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#define DSI85_CHA_DSI_CLK_RNG 0x12
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#define DSI85_CHB_DSI_CLK_RNG 0x13
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#define DSI85_LVDS_MODE 0x18
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#define DSI85_LVDS_SIGN 0x19
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#define DSI85_LVDS_TERM 0x1A
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#define DSI85_LVDS_ADJUST 0x1B
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#define DSI85_CHA_LINE_LEN_LO 0x20
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#define DSI85_CHA_LINE_LEN_HI 0x21
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#define DSI85_CHB_LINE_LEN_LO 0x22
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#define DSI85_CHB_LINE_LEN_HI 0x23
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#define DSI85_CHA_VERT_LINES_LO 0x24
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#define DSI85_CHA_VERT_LINES_HI 0x25
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#define DSI85_CHB_VERT_LINES_LO 0x26
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#define DSI85_CHB_VERT_LINES_HI 0x27
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#define DSI85_CHA_SYNC_DELAY_LO 0x28
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#define DSI85_CHA_SYNC_DELAY_HI 0x29
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#define DSI85_CHB_SYNC_DELAY_LO 0x2A
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#define DSI85_CHB_SYNC_DELAY_HI 0x2B
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#define DSI85_CHA_HSYNC_WIDTH_LO 0x2C
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#define DSI85_CHA_HSYNC_WIDTH_HI 0x2D
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#define DSI85_CHB_HSYNC_WIDTH_LO 0x2E
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#define DSI85_CHB_HSYNC_WIDTH_HI 0x2F
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#define DSI85_CHA_VSYNC_WIDTH_LO 0x30
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#define DSI85_CHA_VSYNC_WIDTH_HI 0x31
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#define DSI85_CHB_VSYNC_WIDTH_LO 0x32
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#define DSI85_CHB_VSYNC_WIDTH_HI 0x33
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#define DSI85_CHA_HORZ_BACKPORCH 0x34
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#define DSI85_CHB_HORZ_BACKPORCH 0x35
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#define DSI85_CHA_VERT_BACKPORCH 0x36
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#define DSI85_CHB_VERT_BACKPORCH 0x37
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#define DSI85_CHA_HORZ_FRONTPORCH 0x38
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#define DSI85_CHB_HORZ_FRONTPORCH 0x39
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#define DSI85_CHA_VERT_FRONTPORCH 0x3A
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#define DSI85_CHB_VERT_FRONTPORCH 0x3B
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#endif
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